CMOS Digital Integrated Circuits: Analysis and Design continues the well-established tradition of the earlier editions by offering the most comprehensive coverage of digital CMOS circuit design, as well as addressing state-of-the-art technology issues highlighted by the widespread use of nanometer-scale CMOS technologies. In this latest edition, virtually, all chapters have been rewritten - the transistor model equations and device parameters have been revised to reflect the sigificant changes that must be taken into account for new technology generations, and the material has been reinforced with up-to-date examples. The broad-ranging coverage of this textbook starts with the fundamentals of CMOS process technology, and continues with MOS transistor models, basic CMOS gates, interconnect effects, dynamic circuits, memory circuits, arithmetic building blocks, clock and I/O circuits, low-power design techniques, design for manufacturability, and design for testability.

Complementary metal oxide semiconductor (CMOS) digital integrated circuits are the enabling technology for the modern information age. Because of their 'intrinsic features in low-power consumption, large noise margins, and ease of design, CMOS integrated circuits have been widely used to develop random access memory (RAM) chips, microprocessor chips, digital signal processor (DSP) chips, and application-specific integrated circuit (ASIC) chips. The popular use of CMOS cir-cuits continues to grow with the increasing demands for low-power, low-noise inte-grated electronic systems in the development of mobile computing platforms, wearable communication devices, smartphones, and multimedia systems.
Since the field of CMOS integrated circuits is broad, it is conventionally divided into digital CMOS circuits and analog CMOS circuits. This textbook is focused on the CMOS digital integrated circuits. However, it should be noted that the boundary between classical digital and analog CMOS design is becoming increasingly blurred, especially with the challenges presented by nanometer-scale fabrication technolo-gies, very low operating voltages, and operating frequencies extending well into the multi-GHz range. Therefore, we attempt to present the analysis and design of digital CMOS integrated circuits from an "analog" point-of-view, i.e., taking into account the analog, non-discrete nature of the devices and circuits that are used to implement digital functions.
The origins of this textbook date back to the early 1990s, when the first two authors were intensively involved in undergraduate-and graduate-level teaching of digital IC fundamentals. At the University of Illinois at Urbana-Champaign, where both of us were teaching at the time, we tried some of the available textbooks on digital MOS integrated circuits for our senior-level technical elective course, ECE 382-Large Scale Integrated Circuit Design. Students and instructors alike realized, however, that there was a need for a new book with more comprehensive treatment of CMOS digital circuits. Thus, our textbook project was initiated several years ago by assembling our own lecture notes. Since 1993, we have used evolving versions of this material at the University of Illinois at Urbana-Champaign, at Istanbul Technical University, at Worcester Polytechnic Institute, and at the Swiss Federal Institute of Technology in Lausanne. We are both encouraged by comments from our students, colleagues, and re-viewers. The first edition of CMOS Digital Integrated Circuits: Analysis and Design was published in late 1995.
Soon after publishing the first edition, we saw the need for updating it to reflect the many constructive comments we were receiving from instructors and students who used the textbook. We intended to include and update important topics such as low-power circuit design and interconnects in high-speed circuit design, as well as the deep sub-micron circuit design issues, and to provide more rigorous treatment of new develop-ments in memory circuits. We also felt that in a rapidly developing field such as CMOS digital circuits, the quality of a textbook can only be preserved by timely updates re-flecting the state of the art. This realization has led us to embark on the successive revi-sions of our work, with the second edition appearing in 1998 and the third edition in 2002, to reflect the advances in technology and in circuit design practices.
During the 11 years that have passed since the publication of the third edition in 2002, the domain of CMOS digital integrated circuits has continued to grow and develop at a never-increasing pace. The advent of nanometer-scale technologies and the widespread use of system-on-chip architectures combining a large number of functional blocks on chip have ushered in dramatic changes in the way digital CMOS integrated circuit design has to be treated. Thus, we came to the conclusion that in-cremental revisions would no longer do justice for the next edition of this textbook, and that we needed a comprehensive rewriting of virtually all chapters. The author team was expanded by the valuable addition of Professor Chulwoo Kim of Korea University, and an extensive revision was embarked upon. The fourth edition is the outcome of this intensive effort.
CMOS Digital Integrated Circuits: Analysis and Design is intended primarily as a comprehensive textbook at the senior level and first-year graduate level, as well as a reference for practicing engineers in the areas of integrated circuit design, digi-tal design, and VLSI. Recognizing that the area of digital integrated circuit design is evolving at an increasingly faster pace, we have made our best effort to present up-to-date materials on all subjects covered. This textbook contains 15 chapters; we recognize that it would not be possible to cover rigorously all of this material in one semester. Thus, we would propose the following based on our teaching experience: At the undergraduate level, coverage of the first 10 chapters would constitute suffi-cient material for a one-semester course on CMOS digital integrated circuits.
Time permitting, some selected topics in Chapter 11, "Low-Power CMOS Logic Circuits," Chapter 12, "Arithmetic Building Blocks," and Chapter 13, "Clock and I/O Circuits" could also be covered. Alternatively, this book could be used for a two-semester course, allowing a more detailed treatment of advanced issues, which are presented in the later chapters. At the graduate level, selected topics from the first 10 chapters plus the last 5 chapters can be covered in one semester.
The first 8 chapters of this textbook are devoted to a detailed treatment of the MOS transistor with all its relevant aspects; to the static and dynamic operation prin-ciples, analysis, and design of basic inverter circuits; and to the structure and opera-tion of combinational and sequential logic gates. Note that the introduction chapter has been significantly expanded to include a detailed presentation of VLSI design methodologies. Since the digital integrated circuit design techniques discussed in the first half of this textbook are directly relevant for digital VLSI and ASIC design, we felt that the context should be presented at the beginning of the book. The issues of on-chip interconnect modeling and interconnect delay calculation are covered exten-sively in Chapter 6, which provides a complete view of switching characteristics in digital integrated circuits. A separate chapter (Chapter 9) has been reserved for the treatment of dynamic logic circuits, which are used in state-of-the-art VLSI chips. Chapter 10 has been completely revised in both content and presentation; it offers an in-depth presentation of many state-of-the-art semiconductor memory circuits.
Recognizing the increasing importance of low-power circuit design, we dedicate one chapter (Chapter 11) to low-power CMOS logic circuits, which provides a com-prehensive coverage of methodologies and design practices that are used to reduce the power dissipation of large-scale digital integrated circuits. Key arithmetic build-ing blocks a represented in Chapter 12, with an emphasis on high-performance multi-bit adders and multipliers.
Next, Chapter 13 provides a clear insight into the important subjects of clocking and chip I/O design. Critical issues such as ESD protection, clock distribution, clock buffering, and latch-up phenomena are discussed in detail. Finally, the more advanced but important topics of design for manufacturability and design for testability are covered in Chapters 14 and 15, respectively.
We have long debated the coverage of nMOS circuits in this textbook. We have concluded that some coverage should be provided for pedagogical reasons. Thus, to emphasize the load concept, which is still widely used in many areas in digital circuit design, we present basic resistive-load and pseudo-nMOS inverter circuits along with their CMOS counterparts in Chapter 5, while we present pseudo-nMOS logic gates (NAND/NOR) in Chapter 7.
The Online Learning Center for this edition (www.mhhe.com/kang) also contains:
An Instructors Manual
Lecture Slides (PowerPoint and PDF)
CadenceTM Design Tutorial
Color Plates.
This text is available as an eBook at www.CourseSmart.com.At Course Smart you can take advantage of significant savings off the cost of a print textbook, reduce their impact on the environment, and gain access to powerful web tools for learning. Course Smart eBooks can be viewed online or downloaded to a com-puter. The eBooks allow readers to do full text searches, add highlighting and notes, and share notes with others. CourseSmart has the largest selection of eBooks available anywhere. Visitwww.CourseSmart.com to learn more and to try a sample chapter.
With McGraw-Hill CreateTM, you can easily rearrange chapters, com-bine material from other content sources, and quickly upload content you have writ-ten, like your course syllabus or teaching notes. Find the content you need in Create by searching through thousands of leading McGraw-Hill textbooks. Arrange your book to fit your teaching style. Create even allows you to personalize your book's ap-pearance by selecting the cover and adding your name, school, and course informa-tion. Order a Create book and you'll receive a complimentary print review copy in 3-5 business days or a complimentary electronic review copy (eComp) via e-mail in minutes. Go to www.mcgrawhillcreate.com today and register to experience how McGraw-Hill Create empowers you to teach your students your way.
Although an immense amount of effort and attention to detail were expended to prepare the camera-ready manuscript, this textbook may still have some flaws and mistakes due to erring human nature. We welcome and greatly appreciate suggestions and corrections from readers for the improvement of technical content as well as the presentation style.
ACKNOWLEDGMENTS TO THE FIRST EDITION
Our colleagues have provided many constructive comments and encouragement for the completion of the first edition. Professor Timothy N. Trick, former head of the department of electrical and computer engineering at the University of Illinois at Urbana-Champaign, has strongly supported our efforts from the very beginning. The appointment of Sung-Mo Kangas an associate in the Center for Advanced Study at the University of Illinois at Urbana-Champaign helped to start the process. Yusuf Leblebici acknowledges the full support and encouragement from the department of electrical and electronics engineering at Istanbul Technical University, where he introduced a new digital integrated circuits course based on the early version of this book and received very valuable feedback from his students.
Yusuf Leblebici also thanks the ETA advanced Electronics Technologies Re-search and Development Foundation at Istanbul Technical University for their gen-ero us support. Professor Elyse Rosenbaum and Professor Resve Saleh used the early versions of the manuscript as the textbook for ECE382 at Illinois and provided many helpful comments and corrections, which have been fully incorporated with deep appreciation. Professor Elizabeth Brauer, currently at Northern Arizona University, has also done the same at the University of Kentucky.
The authors would like to express sincere gratitude to Professor Janak Patel of the University of Illinois at Urbana-Champaign for generously mentoring the authors in writing Chapter 15, "Design for Testability." Professor Patel has provided many constructive comments, and many of his expert views on the subject are reflected in this chapter. Professor Prith Banerjee of Northwestern University and Professor Farid Najm of the University of Illinois at Urbana-Champaign also provided many good comments. We would also like to thank Dr. Abhijit Dharchoudhury for his in-valuable contribution to Chapter 14, "Design for Manufacturability."
Professor Duran Leblebici of Istanbul Technical University, who is the father of the second author, reviewed the entire manuscript in its early development phase, and provided very extensive and constructive comments, many of which are reflected in the final version. Both authors gratefully acknowledge his support during all stages of this venture. We also thank Professor Cem Göknar of Istanbul Technical University, who offered very detailed and valuable comments on "Design for Testability," and Professor Ugur Cilingiroglu of the same university, who offered many excellent suggestions for improving the manuscript, especially the chapter on semiconductor memories.
Many of the authors' former and current students at the University of Illinois at Urbana-Champaign also helped in the preparation of figures and verification of circuits using SPICE simulations. In particular, Dr. James Morikuni, Dr. Weishi Sun, Dr. Pablo Mena, Dr. Jaewon Kim, Mr. Steve Ho, and Mr. Sueng-Yong Park deserve recognition. Ms. Lilian Beck and the staff members of the Publications Office in the department of electrical and computer engineering at the University of Illinois at Urbana-Champaign read the entire manuscript and provided excellent editorial comments.
The authors would also like to thank Dr. Masakazu Shoji of AT&T Bell Labora-tories, Professor Gerold W. Neudeck of Purdue University, Professor Chin-Long Wey of Michigan State University, Professor Andrew T. Yang of the University of Washington, Professor Marwan M. Hassoun of Iowa State University, Professor Charles E. Stroud of the University of Kentucky, Professor Lawrence Pileggi of the University of Texas at Austin, and Professor Yu Hen Hu of the University of Wisconsin at Madison, who read all or parts of the manuscript and provided many valuable comments and encouragement.
The editorial staff of McGraw-Hill has been an excellent source of strong support from the beginning of this textbook project. The venture was originally initiated with the enthusiastic encouragement from the previous electrical engineering editor, Ms. Anne (Brown) A kay. Mr. George Hoffman, inspite of his relatively short associ-ation, was extremely effective and helped settle the details of the publication planning.
During the last stage, the new electrical engineering editor, Ms. Lynn Cox, and Mr. John Morriss, Mr. David Damstra, and Mr. Norman Pedersen of the editing department were superbly effective and we enjoyed dashing with them to finish the last mile.
ACKNOWLEDGMENTS TO THE SECOND EDITION
The authors are truly indebted to many individuals who, with their efforts and their help, made the second edition possible. We would like to thank Dr. Wolfgang Fichtner, President and CEO of ISE Integrated Systems Engineering, Inc., and the technical staff of ISE in Zurich, Switzerland, for providing computer-generated cross-sectional color graphics of MOS transistors and CMOS inverters, which are featured in the color plates. The first author acknowledges the support provided by the U.S. Senior Scientist Research Award from the Alexander von Humbold Stiftung in Germany, which was very helpful for the second edition. The appointments of the second author as Associ-ate Professor at Worcester Polytechnic Institute and as Visiting Professor at the Swiss Federal Institute of Technology in Lausanne, Switzerland have provided excellent en-vironments for the completion of the revision project. The second author also thanks Professor Daniel Mlynek of the Swiss Federal Institute of Technology in Lausanne for his continuous encouragement and support. Many of the authors' former and current students at the University of Illinois at Urbana-Champaign, at the Swiss Federal Insti-tute of Technology in Lausanne, and at Worcester Polytechnic Institute also helped in the preparation of figures and verification of circuits using SPICE simulations. In par-ticular, Dr. James Stroming and Mr. Frank K. Gürkaynak deserve special recognition for their extensive and valuable efforts.
The authors would also like to thank Professor Charles Kime of the University of Wisconsin at Madison, Professor Gerold W. Neudeck of Purdue University, Professor D. E. Ioannou of George Mason University, Professor Subramanya Kalkur of the Uni-versity of Colorado, Professor Jeffrey L. Gray of Purdue University, Professor Jacob Abraham of the University of Texas at Austin, Professor Hisham Z. Massoud of Duke University, Professor Norman C. Tien of Cornell University, Professor Rod Beresford of Brown University, Professor Elizabeth J. Brauer of Northern Arizona University, Professor Reginald J. Perry of Florida State University, and Professor Cem Göknar of Istanbul Technical University who read all or parts of the revised manuscript and provided their valuable comments and encouragement.
The editorial staff of McGraw-Hill has, as always, been wonderfully supportive from the beginning of the revision project. We thankfully recognize the contributions of our previous electrical engineering editor, Ms. Lynn Cox, and we appreciate the extensive efforts of Ms. Nina Kreiden, who helped the project get off the ground in its early stages. During the final stages of this project, Ms. Kelley Butcher, Ms. Karen Nelson, and Mr. Francis Owens were extremely effective and helpful, and we enjoyed sharing this experience with them.
ACKNOWLEDGMENTS TO THE THIRD EDITION
Several individuals have contributed their time and efforts to the third edition of our textbook. The authors would like to acknowledge the invaluable contribution of Dr. Seung-Moon Yoo who was instrumental in the extensive revision of the Memory chapter (Chapter 10). His technical insight, his meticulous attention to detail, and his very productive work are truly appreciated. The first author acknowledges the University of California at Santa Cruz for valuable support in his new position as Dean of the School of Engineering, and for enabling him to concentrate on the revision of the manuscript. The appointment of the second author as Full Professor at the Swiss Federal Institute of Tech-nology in Lausanne, Switzerland, has also provided an excellent environment for the completion of the project. The second author gratefully acknowledges Mme. Severine Eggli for her valuable assistance in revisions, and for typing sections of the text. The au-thors thank Mr. Tom Vernier and the technical staff of the MOSIS organization for gener-ously providing the SPICE B SIM parameters for the TSMC 0.18μm process that were extracted by MOSIS. The authors also acknowledge Dr. Michael W. Davidson of the Florida State University National High Magnetic Field Laboratory, for providing the DEC Alpha chip microphotographs that appear on the cover.
The authors would like to thank the following individuals who read all or parts of the revised manuscript and provided their valuable comments and encouragement.
Professor Massoud Pedram, University of Southern California
Professor E by G. Friedman, University of Rochester
Professor Chien-In Henry Chen, Wright State University
Professor Ivan Kourtev, University of Pittsburgh
Professor Dimitris E. Ioannou, George Mason University
Professor Thottam S. Kalkur, University of Colorado at Colorado Springs
Professor Yong-Bin Kim, Northeastern University
Professor Pratap a Reddy, Rochester Institute of Technology
Professor Hisham Z. Massoud, Duke University
Professor Resve A. Saleh, University of British Columbia
Professor Simon Foo, Florida State University
Professor David W. Parent, San Jose State University
Professor Jaime Ramirez-Angulo, New Mexico State University
Professor Nur Touba, University of Texas at Austin
Professor Nicholas C. Rum in, McGill University
The editorial staff of McGraw-Hill has again been very helpful and supportive through-out the entire revision project. This project started with the insightful initiative of Mr. Tom Casson, our publisher at McGraw-Hill. We would like to acknowledge his valuables up-port and encouragement. We thankfully recognize the contributions of Ms. Michelle Flomenhoft, Ms. Betsy Jones, and Ms. Rose Koos. We especially thank them for their helpful assistance during all stages of this complex project, and for their patience and per-sistence. We also acknowledge Mr. Rick Noel for creating the cover design of the third edition. We truly enjoyed sharing this experience with the entire McGraw-Hill team.
ACKNOWLEDGMENTS TO THE FOURTH EDITION
Perhaps more pronounced than in the previous editions, this fourth edition has bene-fited from the valuable contributions of a number of colleagues and co-workers. As in the third edition, Dr. Seung-Moon Yoo has played a key role in the extensive revision of the Memory chapter (Chapter 10). His technical insight, his meticulous attention to detail, and his productive work are truly appreciated. The first author acknowledges the University of California system for its support for administrative leave, which en-abled focused effort for the revision, and many colleagues in the Department of Elec-trical Engineering at the Korea Advanced Institute of Science and Technology (KAIST) who encouraged and supported the final phase of this revision.
The second author acknowledges the Swiss Federal Institute of Technology in Lausanne, Switzerland, for providing an excellent environment for the completion of the project. The third author acknowledges the Korea University in Seoul, Korea, for enabling him to finish the revision.
A number of students at Korea University helped in the preparation of figures, SPICE simulations, and layout. Special recognition goes to Dr. Young-Ho Kwak, Dr. Phi-Hung Pham, Dr. Moo-Young Kim, Dr. Inhwa Jung, Dr. Minyoung Song, Mr. Hokyu Lee, Mr. Jungmoon Kim, Mr. Junyoung Song, and Mr. Sewook Hwang.
The authors thank Professor Rhett Davis at North Carolina State University for let-ting us use freePDK45TM for layout and Professor Yu Cao at Arizona State University for PTM SPICE B SIM parameters for 65-nm process (http://ptm.asu.edu/). We devel-oped our own parameters based on that and used it for simulations in this textbook
The authors would like to thank the following individuals who read all or parts of the revised manuscript and provided their valuable comments and encouragement.
Khalid H. A bed, Jackson State University
Erik Cheever, Swarthmore College
Frank T. Duda Jr., Grove City College
Kali app an Gopalan, Purdue University-Calumet
Yong-Bin Kim, Northeastern University
Selahattin Sayil, Lamar University
Nur Touba, University of Texas-Austin
Syed Kamrul Islam, University of Tennessee
Simon Y. Foo, Florida State University
Rizwan Bashirullah, University of Florida
Wagdy Mahmoud, University of the District of Columbia
Azadeh Davoodi, University of Wisconsin
John Loomis, University of Dayton
The editorial staff of McGraw-Hill has again been helpful and supportive throughout the entire revision project. We especially acknowledge the contributions of Mr. Raghu Srinivasan, Ms. Darlene Schuller, Ms. Lisa Bruflodt, and Mr. Vincent Bradshaw, for their valuable assistance during all stages of this complex project, and for their patience and persistence. We truly enjoyed sharing this experience with the entire McGraw-Hill team.
Finally, we would like to acknowledge the support from our families, M young-A (Mia) , Jennifer, and Jeffrey Kang and Victoria Tung, Anil and Ebru Leblebici, and Mi-Soon Choi, Minjin, and Doyeon Kim, for tolerating many of our physical and mental absences while we worked on the fourth edition of this textbook, and for pro-viding us invaluable encouragement throughout the project.
Sung-Mo (Steve) Kang Daejeon, Korea August 2013
Yusuf Leblebici Lausanne, Switzerland August 2013
Chluwoo Kim Seoul, Korea August 2013

About the Authors ix

Preface xi

1 Introduction 1

2 Fabrication of MOSFETs 49

3 MOS Transistor 92

4 Modeling of MOS Transistors Using SPICE 167

5 MOS Inverters: Static Characteristics 194

6 MOS Inverters: Switching Characteristics and Interconnect Effects 245

7 Combination alMOS Logic Circuits 305

8 Sequential MOS Logic Circuits 356

9 Dynamic Logic Circuits 398

10 Semiconductor Memories 447

11 Low-Power CMOS Logic Circuits 527

12 Arithmetic Building Blocks 569

13 Clock and I/O Circuits 592

14 Design for Manufacturability 633

15 Design for Testability 670

References 685

Index 691

Color Plates CP-1

About the Author six

Preface xi

Chapter 1

Introduction 1

1.1 Historical Perspective 1

1.2 Objective and Organization of the Book 5

1.3 A Circuit Design Example 8

1.4 Overview of VLSI Design Methodologies 18

1.5 VLSI Design Flow 20

1.6 Design Hierarchy 23

1.7 Concepts of Regularity, Modularity, and Locality 26

1.8 VLSI Design Styles 28

1.9 Design Quality 39

1.10 Packaging Technology 41

1.11 Computer-Aided Design Technology 44

      Exercise Problems 46

Chapter 2

Fabrication of MOSFETs 49

2.1 Introduction 49

2.2 Fabrication Process Flow: Basic Steps 50

2.3 The CMOS n-Well Process 60

2.4 Evolution of CMOS Technology 67

2.5 Layout Design Rules 74

2.6 Full-Custom Mask Layout Design 78

      Exercise Problems 82

Chapter 3

MOS Transistor 92

3.1 The Metal Oxide Semiconductor (MOS) Structure 92

3.2 The MOS System Under External Bias 96

3.3 Structure and Operation of the MOS Transistor (MOSFET) 99

3.4 MOSFET Current-Voltage Characteristics 109

3.5 MOSFET Scaling and Small-Geometry Effects 120

3.6 MOSFET Capacitances 151

      Exercise Problems 162

Chapter 4

Modeling of MOS Transistors Using SPICE

4.1 Introduction

4.2 Basic Concepts

4.3 The Level l Model Equations

4.4 The Level 2 Model Equations

4.5 The Level 3 Model Equations

4.6 State-of-the-Art MOSFET Models

4.7 Capacitance Models180

4.8 Comparison of the SPICE MOSFET Models184

      Appendix: Typical SPICE Model Parameters186

      Exercise Problems192

Chapter 5

MOS Inverters: Static Characteristics 194

5.1 Introduction 194

5.2 Resistive-Load Inverter 202

5.3 Inverters with MOSFET Load 211

5.4 CMOS Inverter 221

      Appendix: Sizing Trends of CMOS Inverter with Small-Geometry Devices 239

      Exercise Problems 241

Chapter 6

MOS Inverters: Switching Characteristics and Interconnect Effects 245

6.1 Introduction 245

6.2 Delay-Time Definitions 247

6.3 Calculation of Delay Times 249

6.4 Inverter Design with Delay Constraints 257

6.5 Estimation of Interconnect Parasitics 267

6.6 Calculation of Interconnect Delay 280

6.7 Switching Power Dissipation of CMOS Inverters 288

      Appendix: Super Buffer Design 297

      Exercise Problems 300

Chapter 7

Combinational MOS Logic Circuits 305

7.1 Introduction 305

7.2 MOS Logic Circuits with Pseudo-nMOS (pMOS) Loads 306

7.3 CMOS Logic Circuits 319

7.4 Complex Logic Circuits 326

7.5 CMOS Transmission Gates (Pass Gates) 339

      Exercise Problems 349

Chapter 8

Sequential MOS Logic Circuits 356

8.1 Introduction 356

8.2 Behavior of Bistable Elements 357

8.3 The SR Latch Circuit 363

8.4 Clocked Latch and Flip-Flop Circuits 368

8.5 Timing-Related Parameters of Clocked Storage Elements 376

8.6 CMOS D-Latch and Edge-Triggered Flip-Flop 378

8.7 Pulsed Latch-Based Clocked Storage Elements 384

8.8 Sense-Amplifier-Based Flip-Flops 386

8.9 Logic Embedding in Clocked Storage Elements 388

8.10 Power Consumption of Clocking System and Power Savings Methodologies 389

      Appendix 391

      Exercise Problems 394

Chapter 9

Dynamic Logic Circuits 398

9.1 Introduction 398

9.2 Basic Principles of Pass Transistor Circuits 400

9.3 Voltage Bootstrapping 412

9.4 Synchronous Dynamic Circuit Techniques 416

9.5 Dynamic CMOS Circuit Techniques 421

9.6 High-Performance Dynamic CMOS Circuits 425

      Exercise Problems 442

Chapter 10

Semiconductor Memories 447

10.1 Introduction 447

10.2 Dynamic Random Access Memory (DRAM) 452

10.3 Static Random Access Memory (SRAM) 481

10.4 Nonvolatile Memory 497

10.5 Flash Memory 510

10.6 Ferroelectric Random Access Memory (FRAM) 518

      Exercise Problems 521

Chapter 11

Low-Power CMOS Logic Circuits 527

11.1 Introduction 527

11.2 Overview of Power Consumption 528

11.3 Low-Power Design Through Voltage Scaling 541

11.4 Estimation and Optimization of Switching Activity 552

11.5 Reduction of Switched Capacitance 558

11.6 Adiabatic Logic Circuits 560

      Exercise Problems 568

Chapter 12

Arithmetic Building Blocks 569

12.1 Introduction 569

12.2 Adder 569

12.3 Multipliers 580

12.4 Shifter 586

      Exercise Problems 588

Chapter 13

Clock and I/O Circuits 592

13.1 Introduction 592

13.2 ESD Protection 592

13.3 Input Circuits 596

13.4 Output Circuits and L (di/dt) Noise 600

13.5 On-Chip Clock Generation and Distribution 605

13.6 Latch-Up and Its Prevention 620

      Appendix: Network-on-Chip: An Emerging Paradigm for Next-Generation SoCs 627

      Exercise Problems 631

Chapter 14

Design for Manufacturability 633

14.1 Introduction 633

14.2 Process Variations 634

14.3 Basic Concepts and Definitions 636

14.4 Design of Experiments and Performance Modeling 642

14.5 Parametric Yield Estimation 650

14.6 Parametric Yield Maximization 655

14.7 Worst-Case Analysis 657

14.8 Performance Variability Minimization 663

      Exercise Problems 666

Chapter 15

Design for Testability 670

15.1 Introduction 670

15.2 Fault Types and Models 670

15.3 Controllability and Observability 674

15.4 Ad Hoc Testable Design Techniques 675

15.5 Scan-Based Techniques 678

15.6 Built-In Self-Test (BIST) Techniques 680

15.7 Current Monitoring IDDQ Test Exercise Problems 683

      Exercise Problems 684

References 685

Index 691

Color Plates CP-1

Chulwoo Kim received BS and MS degrees in electronics engineering from Korea University, and a PhD in electrical and computer engineering from the Uni-versity of Illinois at Urbana-Champaign. In 1999, he worked as a summer intern at Design Technology at Intel Corporation, Santa Clara, California. In May 2001, he joined IBM Microelectronics Division in Austin, Texas, where he was involved in cell processor design. Since September 2002, he has been with the Department of Elec-tronics and Computer Engineering at Korea University, where he is currently a pro-fessor. He was a visiting professor at the University of California, Los Angeles and at the University of California, Santa Cruz. His current research interests are in the areas of wireline transceiver, memory, power management, and data converters. PA\Dr. Kim received the Samsung Human Tech Thesis Contest Bronze Award, the ISLPED Low-Power Design Contest Award, the DAC Student Design Contest Award, the SRC Inventor Recognition Award, the Young Scientist Award from the Ministry of Science and Technology of Korea, the Seoktop Award for excellence in teaching, and the ASP-DAC Best Design Award. He is currently on the editorial board of IEEE Transactions on VLSI Systems and on the Technical Program Com-mittee of the IEEE International Solid-State Circuits Conference.

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