This book is intended for an introductory course in digital logic design, which 1s a basiccourse in most electrical and computer engineering programs. A successful designer ofdigital logic circuits needs a good understanding of basic concepts and a firm grasp of themodern design approach that relies on computer-aided design (CAD) tools.
The main goals of the book are (1) to teach students the fundamental concepts in- classical manual digital design and (2) illustrate clearly the way in which digital circuitsare designed today, using CAD tools. Even though modern designers no longer use manualtechniques, except in rare circumstances, our motivation for teaching such techniques is: to give students an intuitive feeling for how digital circuits operate. Also. the manual techniques provide an illustration of the types of manipulations performed by CAD tovls.giving students an appreciation of the benefits provided by design automation. Throughoutthe book, basic concepts are introduced by way of examples that involve simple circuitdesigns, which we perform using both manual techniques and modern CAD-tool-basedmethods. Having established the basic concepts, more complex examples are then provided.using the CAD tools. Thus our emphasis is on modern design methodology to illustratehow digital design is carried out in practice today.

Chapter 1 Introduction 1 

第1章 绪论1 

1.1 Digital Hardware 2 

1.1 数字硬件 2 

      1.1.1 Standard Chips 4 

      1.1.1 标准芯片 4 

      1.1.2 Programmable Logic Devices 5 

      1.1.2 可编程逻辑器件 5 

      1.1.3 CustomDesigned Chips 5 

      1.1.3 定制芯片5 

1.2 The Design Process 6 

1.2 设计过程 6 

1.3 Structure of a Computer 8 

1.3 计算机结构 8 

1.4 Logic Circuit Design in This Book 8 

1.4 本书中的逻辑电路设计 8 

1.5 Digital Representation of Information 11 

1.5 信息的数字表示 11 

      1.5.1 Binary Numbers 12 

      1.5.1 二进制数 12 

      1.5.2 Conversion between Decimal and Binary Systems 13 

      1.5.2 十进制和二进制系统之间的转换 13 

      1.5.3 ASCII Character Code 14 

      1.5.3 ASCII字符码 14 

      1.5.4 Digital and Analog Information 16 

      1.5.4 数字和模拟信息 16 

1.6 Theory and Practice 16 

1.6 理论和实践 16 

Problems 18 

习题 18 

References 19 

参考文献 19 

Chapter 2 Introduction to Logic Circuits 21 

第2章 逻辑电路导论 21 

2.1 Variables and Functions 22 

2.1 变量和函数 22 

2.2 Inversion 25 

2.2 反相 25 

2.3 Truth Tables 26 

2.3 真值表 26 

2.4 Logic Gates and Networks 27 

2.4 逻辑门和网络 27 

      2.4.1 Analysis of a Logic Network 29 

      2.4.1 逻辑网络的分析 29 

2.5 Boolean Algebra 33 

2.5 布尔代数 33 

      2.5.1 The Venn Diagram 37 

      2.5.1 维恩图 37 

      2.5.2 Notation and Terminology 42 

      2.5.2 符号和术语 42 

      2.5.3 Precedence of Operations 43 

      2.5.3 操作的优先级 43 

2.6 Synthesis Using AND, OR, and NOT Gates 43 

2.6 用与、或和非门进行综合 43 

      2.6.1 SumofProducts and Product of Sums Forms 48 

      2.6.1 与或和或与形式 48 

2.7 NAND and NOR Logic Networks 54 

2.7 与非和或非逻辑网络 54 

2.8 Design Examples 59 

2.8 设计实例 59 

      2.8.1 ThreeWay Light Control 59 

      2.8.1 三路灯光控制 59 

      2.8.2 Multiplexer Circuit 60 

      2.8.2 多路选择器电路 60 

      2.8.3 Number Display 63 

      2.8.3 数字显示 63 

2.9 Introduction to CAD Tools 64 

2.9 CAD工具简介 64 

      2.9.1 Design Entry 64 

      2.9.1 设计输入 64 

      2.9.2 Logic Synthesis 66 

      2.9.2 逻辑综合 66 

      2.9.3 Functional Simulation 67 

      2.9.3 功能仿真 67 

      2.9.4 Physical Design 67 

      2.9.4 物理设计 67 

      2.9.5 Timing Simulation 67 

      2.9.5 时序仿真 67 

      2.9.6 Circuit Implementation 68 

      2.9.6 电路实现 68 

      2.9.7 Complete Design Flow 68 

      2.9.7 完整的设计流程 68 

2.10 Introduction to Verilog 68 

2.10 Verilog简介 68 

      2.10.1 Structural Specification of Logic Circuits 70 

      2.10.1 逻辑电路的结构描述 70 

      2.10.2 Behavioral Specification of Logic Circuits 72 

      2.10.2 逻辑电路的行为描述 72 

      2.10.3 Hierarchical Verilog Code 76 

      2.10.3 层次化Verilog代码 76 

      2.10.4 How NOT to Write Verilog Code 78 

      2.10.4 如何不写Verilog代码 78 

2.11 Minimization and Karnaugh Maps 78 

2.11 化简和卡诺图 78 

2.12 Strategy for Minimization 87 

2.12 化简策略 87 

      2.12.1 Terminology 87 

      2.12.1 术语 87 

      2.12.2 Minimization Procedure 89 

      2.12.2 化简过程 89 

2.13 Minimization of Product of Sums Forms 91 

2.13 或与形式的最简 91 

2.14 Incompletely Specified Functions 94 

2.14 不完全确定函数 94 

2.15 MultipleOutput Circuits 96 

2.15 多输出电路 96 

2.16 Concluding Remarks 101 

2.16 小结 101 

2.17 Examples of Solved Problems 101 

2.17 问题求解案例 101 

Problems 111 

习题 111 

References 120 

参考文献 120 

Chapter 3 Number Representation and Arithmetic Circuits 121 

第3章 数的表示和算术电路 121 

3.1 Positional Number Representation 122 

3.1 数位表示法 122 

      3.1.1 Unsigned Integers 122 

      3.1.1 无符号整数 122 

      3.1.2 Octal and HexadecimalRepresentations 123 

      3.1.2 八进制数和十六进制数的表示 123 

3.2 Addition of Unsigned Numbers 125 

3.2 无符号数的加法 125 

      3.2.1 Decomposed Full Adder 129 

      3.2.1 全加器的分解 129 

      3.2.2 RippleCarry Adder 129 

      3.2.2 行波进位加法器 129 

      3.2.3 Design Example 130 

      3.2.3 设计实例 130 

3.3 Signed Numbers 132 

3.3 有符号数 132 

      3.3.1 Negative Numbers 133 

      3.3.1 负数 133 

      3.3.2 Addition and Subtraction 135 

      3.3.2 加法和减法 135 

      3.3.3 Adder and Subtractor Unit 138 

      3.3.3 加法器和减法器单元 138 

      3.3.4 RadixComplement Schemes 139 

      3.3.4 基数补码方案 139 

      3.3.5 Arithmetic Overflow 143 

      3.3.5 算术溢出 143 

      3.3.6 Performance Issues 145 

      3.3.6 性能问题 145 

3.4 Fast Adders145 

3.4 快速加法器 145 

      3.4.1 CarryLookahead Adder 146 

      3.4.1 超前进位加法器 146 

3.5 Design of Arithmetic Circuits Using CAD Tools 151 

3.5 用CAD工具设计算术电路 151 

      3.5.1 Design of Arithmetic Circuits Using Schematic Capture 151 

      3.5.1 用原理图编辑工具设计算术电路 151 

      3.5.2 Design of Arithmetic Circuits Using Verilog 152 

      3.5.2 用Verilog设计算术电路 152 

      3.5.3 Using Vectored Signals 155 

      3.5.3 用向量信号 155 

      3.5.4 Using a Generic Specification 156 

      3.5.4 用自动生成语句 156 

      3.5.5 Nets and Variables in Verilog 158 

      3.5.5 Verilog中的线网和变量 158 

      3.5.6 Arithmetic Assignment Statements 159 

      3.5.6 算术赋值语句 159 

      3.5.7 Module Hierarchy in Verilog Code 163 

      3.5.7 Verilog中的模块层次化 163 

      3.5.8 Representation of Numbers in Verilog Code 166 

      3.5.8 Verilog中数的表示 166 

3.6 Multiplication 167 

3.6 乘法 167 

      3.6.1 Array Multiplier for Unsigned Numbers 167 

      3.6.1 无符号数的阵列乘法 167 

      3.6.2 Multiplication of Signed Numbers 169 

      3.6.2 有符号数的乘法 169 

3.7 Other Number Representations 170 

3.7 其他数的表示 170 

      3.7.1 FixedPoint Numbers 170 

      3.7.1 定点数 170 

      3.7.2 FloatingPoint Numbers 172 

      3.7.2 浮点数 172 

      3.7.3 BinaryCodedDecimal Representation 174 

      3.7.3 二进制编码的十进制数表示 174 

3.8 Examples of Solved Problems 178 

3.8 问题求解案例 178 

Problems 184 

习题 184 

References 188 

参考文献 188 

Chapter 4 CombinationalCircuit Building Blocks 189 

第4章 组合电路构件块 189 

4.1 Multiplexers 190 

4.1 多路选择器 190 

      4.1.1 Synthesis of Logic Functions Using Multiplexers 193 

      4.1.1 用多路选择器进行逻辑函数综合 193 

      4.1.2 Multiplexer Synthesis Using Shannons Expansion 196 

      4.1.2 用香农展开进行多路选择器综合 196 

4.2 Decoders 201 

4.2 译码器 201 

      4.2.1 Demultiplexers 203 

      4.2.1 多路分解器 203 

4.3 Encoders 205 

4.3 编码器 205 

      4.3.1 Binary Encoders 205 

      4.3.1 二进制编码器 205 

      4.3.2 Priority Encoders 205 

      4.3.2 优先编码器 205 

4.4 Code Converters 208 

4.4 码制转换器 208 

4.5 Arithmetic Comparison Circuits 208 

4.5 算术比较电路 208 

4.6 Verilog for Combinational Circuits 210 

4.6 用Verilog表示组合电路 210 

      4.6.1 The Conditional Operator 210 

      4.6.1 条件操作符 210 

      4.6.2 The IfElse Statement 212 

      4.6.2 ifelse语句 212 

      4.6.3 The Case Statement 215 

      4.6.3 case语句 215 

      4.6.4 The For Loop 221 

      4.6.4 for循环语句 221 

      4.6.5 Verilog Operators 223 

      4.6.5 Verilog操作符 223 

      4.6.6 The Generate Construct 228 

      4.6.6 生成结构 228 

      4.6.7 Tasks and Functions 229 

      4.6.7 任务和函数 229 

4.7 Concluding Remarks 232 

4.7 小结 232 

4.8 Examples of Solved Problems 233 

4.8 问题求解案例 233 

Problems 243 

习题 243 

References 246 

参考文献 246 

Chapter 5 FlipFlops, Registers, and Counters 247 

第5章 触发器、寄存器和计数器 247 

5.1 Basic Latch249 

5.1 基本锁存器 249 

5.2 Gated SR Latch 251 

5.2 门控SR锁存器 251 

      5.2.1 Gated SR Latch with NAND Gates 253 

      5.2.1 用与非门实现的门控SR锁存器 253 

5.3 Gated D Latch 253 

5.3 门控D锁存器 253 

      5.3.1 Effects of Propagation Delays 255 

      5.3.1 传输延时的影响 255 

5.4 EdgeTriggered D FlipFlops 256 

5.4 边沿触发的D触发器 256 

      5.4.1 MasterSlave D FlipFlop 256 

      5.4.1 主从D触发器 256 

      5.4.2 Other Types of EdgeTriggered D FlipFlops 258 

      5.4.2 其他类型的边沿触发的D触发器 258 

      5.4.3 D FlipFlops with Clear and Preset 260 

      5.4.3 带清零和置位的D触发器 260 

      5.4.4 FlipFlop Timing Parameters 263 

      5.4.4 触发器的时间参数 263 

5.5 T FlipFlop 263 

5.5 T触发器 263 

5.6 JK FlipFlop 264 

5.6 JK触发器 264 

5.7 Summary of Terminology 266 

5.7 术语小结 266 

5.8 Registers 267 

5.8 寄存器 267 

      5.8.1 Shift Register 267 

      5.8.1 移位寄存器 267 

      5.8.2 ParallelAccess Shift Register 267 

      5.8.2 并行存取的移位寄存器 267 

5.9 Counters 269 

5.9 计数器269 

      5.9.1 Asynchronous Counters 269 

      5.9.1 异步计数器 269 

      5.9.2 Synchronous Counters272 

      5.9.2 同步计数器 272 

      5.9.3 Counters with Parallel Load 276 

      5.9.3 可并行置数的计数器 276 

5.10 Reset Synchronization 278 

5.10 同步复位 278 

5.11 Other Types of Counters 280 

5.11 其他类型的计数器 280 

      5.11.1 BCD Counter 280 

      5.11.1 BCD计数器 280 

      5.11.2 Ring Counter 280 

      5.11.2 环形计数器 280 

      5.11.3 Johnson Counter 283 

      5.11.3 约翰森（Johnson）计数器 283 

      5.11.4 Remarks on Counter Design 283 

      5.11.4 计数器设计小结 283 

5.12 Using Storage Elements with CAD Tools 284 

5.12 CAD工具中存储单元的使用 284 

      5.12.1 Including Storage Elements in Schematics 284 

      5.12.1 在原理图中加入存储单元284 

      5.12.2 Using Verilog Constructs for Storage Elements 285 

      5.12.2 用Verilog代码实现存储单元 285 

      5.12.3 Blocking and NonBlocking Assignments 288 

      5.12.3 阻塞和非阻塞赋值 288 

      5.12.4 NonBlocking Assignments for Combinational Circuits 293 

      5.12.4 组合电路的非阻塞赋值 293 

      5.12.5 FlipFlops with Clear Capability 293 

      5.12.5 具有清零功能的触发器 293 

5.13 Using Verilog Constructs for Registers and Counters 295 

5.13 用Verilog代码实现寄存器和计数器 295 

      5.13.1 FlipFlops and Registers with Enable Inputs 300 

      5.13.1 具有使能输入的触发器和寄存器 300 

      5.13.2 Shift Registers with Enable Inputs 302 

      5.13.2 具有使能输入的移位寄存器 302 

5.14 Design Example 302 

5.14 设计案例 302 

      5.14.1 Reaction Timer 302 

      5.14.1 反应计时器 302 

      5.14.2 Register Transfer Level (RTL) Code 309 

      5.14.2寄存器传输级（RTL）代码 309 

5.15 Timing Analysis of Flipflop Circuits 310 

5.15 触发器电路的时序分析 310 

      5.15.1 Timing Analysis with Clock Skew 312 

      5.15.1 有时钟漂移的时序分析 312 

5.16 Concluding Remarks 314 

5.16 小结 314 

5.17 Examples of Solved Problems 315 

5.17 问题求解案例 315 

Problems 321 

习题 321 

References 329 

参考文献 329 

Chapter 6 Synchronous Sequential Circuits 331 

第6章 同步时序电路 331 

6.1 Basic Design Steps 333 

6.1 基本设计步骤 333 

      6.1.1 State Diagram 333 

      6.1.1 状态图 333 

      6.1.2 State Table 335 

      6.1.2 状态表 335 

      6.1.3 State Assignment336 

      6.1.3 状态分配336 

      6.1.4 Choice of Flip Flops and Derivation of NextState and Output Expressions 337 

      6.1.4 触发器的选择以及次态和输出表达式的推导 337 

      6.1.5 Timing Diagram 339 

      6.1.5 时序图 339 

      6.1.6 Summary of Design Steps 340 

      6.1.6 设计步骤小结 340 

6.2 StateAssignment Problem 344 

6.2 状态分配问题 344 

      6.2.1 One Hot Encoding 347 

      6.2.1 单热编码 347 

6.3 Mealy State Model 349 

6.3 米利状态模型 349 

6.4 Design of Finite State Machines Using CAD Tools 354 

6.4 用CAD工具设计有限状态机 354 

      6.4.1 Verilog Code for MooreType FSMs 355 

      6.4.1 摩尔型有限状态机的Verilog代码 355 

      6.4.2 Synthesis of Verilog Code 356 

      6.4.2 Verilog代码的综合 356 

      6.4.3 Simulating and Testing the Circuit 358 

      6.4.3 仿真和测试该电路 358 

      6.4.4 Alternative Styles of Verilog Code 359 

      6.4.4另一种风格的Verilog代码 359 

      6.4.5 Summary of Design Steps When Using CAD Tools 360 

      6.4.5 用CAD工具的设计步骤小结 360 

      6.4.6 Specifying the State Assignment in Verilog Code 361 

      6.4.6 在Verilog代码中进行状态分配 361 

      6.4.7 Specification of Mealy FSMs Using Verilog 363 

      6.4.7用Verilog代码来描述米利有限状态机 363 

6.5 Serial Adder Example 363 

6.5 串行加法器举例 363 

      6.5.1 Mealy Type FSM for Serial Adder 364 

      6.5.1 串行加法器的米利型有限状态机 364 

      6.5.2 MooreType FSM for Serial Adder 367 

      6.5.2 串行加法器的摩尔型有限状态机 367 

      6.5.3 Verilog Code for the Serial Adder 370 

      6.5.3 串行加法器的Verilog代码 370 

6.6 State Minimization 372 

6.6 状态化简 372 

      6.6.1 Partitioning Minimization Procedure 374 

      6.6.1 化简过程的划分 374 

      6.6.2 Incompletely Specified FSMs 381 

      6.6.2 不完全确定的有限状态机 381 

6.7 Design of a Counter Using the Sequential Circuit Approach 383 

6.7 用时序电路方法设计计数器383 

      6.7.1 State Diagram and State Table for a Modulo8Counter 383 

      6.7.1 模8计数器的状态图和状态表 383 

      6.7.2 State Assignment 384 

      6.7.2 状态分配 384 

      6.7.3 Implementation Using DType FlipFlops 385 

      6.7.3 用D触发器实现 385 

      6.7.4 Implementation Using JKType FlipFlops 386 

      6.7.4 用JK触发器实现 386 

      6.7.5 Example—A Different Counter 390 

      6.7.5 案例——一个不一样的计数器 390 

6.8 FSM as an Arbiter Circuit 393 

6.8 用作仲裁器电路的有限状态机 393 

6.9 Analysis of Synchronous Sequential Circuits 397 

6.9 同步时序电路分析 397 

6.10 Algorithmic State Machine (ASM) Charts 401 

6.10 算法状态机（ASM）图 401 

6.11 Formal Model for Sequential Circuits 405 

6.11 时序电路的形式化模型 405 

6.12 Concluding Remarks 407 

6.12 小结 407 

6.13 Examples of Solved Problems 407 

6.13 问题求解案例 407 

Problems 416 

习题 416 

References 420 

参考文献 420 

Chapter 7 Digital System Design 421 

第7章 数字系统设计 421 

7.1 Bus Structure 422 

7.1 总线结构 422 

      7.1.1 Using TriState Drivers to Implement a Bus 422 

      7.1.1 用三态驱动器实现总线 422 

      7.1.2 Using Multiplexers to Implement a Bus 424 

      7.1.2 用多路选择器实现总线 424 

      7.1.3 Verilog Code for Specification of Bus Structures 426 

      7.1.3 总线结构的Verilog代码描述 426 

7.2 Simple Processor 429 

7.2 简单处理器 429 

7.3 A BitCounting Circuit 441 

7.3 位计数电路 441 

7.4 ShiftandAdd Multiplier 446 

7.4 移位相加实现的乘法器 446 

7.5 Divider 455 

7.5 除法器 455 

7.6 Arithmetic Mean 466 

7.6 算术平均 466 

7.7 Sort Operation 470 

7.7 排序操作 470 

7.8 Clock Synchronization and Timing Issues 478 

7.8 时钟同步和时序问题 478 

      7.8.1 Clock Distribution 478 

      7.8.1 时钟偏差 478 

      7.8.2 FlipFlop Timing Parameters 481 

      7.8.2 触发器的时序参数 481 

      7.8.3 Asynchronous Inputs to FlipFlops 482 

      7.8.3 触发器的异步输入482 

      7.8.4 Switch Debouncing 483 

      7.8.4 开关抖动 483 

7.9 Concluding Remarks 485 

7.9 小结 485 

Problems 485 

习题 485 

References 489 

参考文献 489 

Chapter 8 Optimized Implementation of Logic Functions 491 

第8章 逻辑函数的优化实现 491 

8.1 Multilevel Synthesis 492 

8.1 多级综合 492 

      8.1.1 Factoring 493 

      8.1.1 提取公因子 493 

      8.1.2 Functional Decomposition 496 

      8.1.2 函数分解 496 

      8.1.3 Multilevel NAND and NOR Circuits 502 

      8.1.3 多级与非和或非电路 502 

8.2 Analysis of Multilevel Circuits 504 

8.2 多级电路的分析 504 

8.3 Alternative Representations of Logic Functions 510 

8.3 逻辑函数的替代表示 510 

      8.3.1 Cubical Representation 510 

      8.3.1 立方体表示 510 

      8.3.2 Binary Decision Diagrams 514 

      8.3.2 二进制决策图 514 

8.4 Optimization Techniques Based on Cubical Representation 520 

8.4 基于立方体表示的优化技术 520 

      8.4.1 A Tabular Method for Minimization 521 

      8.4.1 化简的列表法 521 

      8.4.2 A Cubical Technique for Minimization 529 

      8.4.2 立方体化简技术 529 

      8.4.3 Practical Considerations 536 

      8.4.3 实际问题考虑 536 

8.5 Concluding Remarks 537 

8.5 小结 537 

8.6 Examples of Solved Problems 537 

8.6 问题求解案例 537 

Problems 546 

习题 546 

References 549 

参考文献 549 

Chapter 9 Asynchronous Sequential Circuits 551 

第9章 异步时序电路 551 

9.1 Asynchronous Behavior 552 

9.1 异步行为 552 

9.2 Analysis of Asynchronous Circuits 556 

9.2 异步电路分析556 

9.3 Synthesis of Asynchronous Circuits 564 

9.3 异步电路综合 564 

9.4 State Reduction 577 

9.4 状态化简 577 

9.5 State Assignment 592 

9.5 状态分配 592 

      9.5.1 Transition Diagram 595 

      9.5.1 转移图 595 

      9.5.2 Exploiting Unspecified NextState Entries 598 

      9.5.2 未指定次态项的利用 598 

      9.5.3 State Assignment Using Additional State Variables 602 

      9.5.3 用附加状态进行的状态分配602 

      9.5.4 OneHot State Assignment 607 

      9.5.4 单热状态分配 607 

9.6 Hazards 608 

9.6冒险 608 

      9.6.1 Static Hazards 609 

      9.6.1 静态冒险 609 

      9.6.2 Dynamic Hazards 613 

      9.6.2 动态冒险 613 

      9.6.3 Significance of Hazards 614 

      9.6.3 冒险的意义 614 

9.7 A Complete Design Example 616 

9.7 一个完整的设计实例 616 

      9.7.1 The VendingMachine Controller 616 

      9.7.1 自动售货机控制器 616 

9.8 Concluding Remarks 621 

9.8 小结 621 

9.9 Examples of Solved Problems 623 

9.9 问题求解案例 623 

Problems 631 

习题 631 

References 635 

参考文献 635 

Chapter 10 Computer Aided Design Tools 637 

第10章 计算机辅助设计工具 637 

10.1 Synthesis 638 

10.1 综合 638 

      10.1.1 Netlist Generation 638 

      10.1.1 网表生成 638 

      10.1.2 Gate Optimization 638 

      10.1.2 门优化 638 

      10.1.3 Technology Mapping 640 

      10.1.3 技术映射 640 

10.2 Physical Design 644 

10.2 物理设计 644 

      10.2.1 Placement 646 

      10.2.1 布局 646 

      10.2.2 Routing 647 

      10.2.2 布线 647 

      10.2.3 Static Timing Analysis 648 

      10.2.3 静态时序分析 648 

10.3 Concluding Remarks 650 

10.3 小结 650 

References 651 

参考文献 651 

Chapter 11 Testing of Logic Circuits 653 

第11章 逻辑电路测试 653 

11.1 Fault Model 654 

11.1 故障模型 654 

      11.1.1 Stuckat Model 654 

      11.1.1 固滞模型 654 

      11.1.2 Single and Multiple Faults 655 

      11.1.2 单个和多个故障 655 

      11.1.3 CMOS Circuits 655 

      11.1.3 CMOS电路 655 

11.2 Complexity of a Test Set 655 

11.2 测试集的复杂度 655 

11.3 Path Sensitizing 657 

11.3 路径的敏感化657 

11.3.1 Detection of a Specific Fault 659 

11.3.1特殊故障的检测 659 

11.4 Circuits with Tree Structure 661 

11.4 树状结构电路 661 

11.5 Random Tests 662 

11.5 随机测试 662 

11.6 Testing of Sequential Circuits 665 

11.6 时序电路测试 665 

11.6.1 Design for Testability 665 

11.6.1 可测试设计 665 

11.7 Built in Self Test 669 

11.7 内建自测试 669 

      11.7.1 Builtin Logic Block Observer 673 

      11.7.1 内建逻辑块观察器 673 

      11.7.2 Signature Analysis 675 

      11.7.2 签字分析 675 

      11.7.3 Boundary Scan 676 

      11.7.3 边界扫描676 

11.8 Printed Circuit Boards 676 

11.8 印制电路板 676 

      11.8.1 Testing of PCBs 678 

      11.8.1PCB测试678 

      11.8.2 Instrumentation 679 

      11.8.2 测试仪器 679 

11.9 Concluding Remarks 680 

11.9 小结 680 

Problems 680 

习题 680 

References 683 

参考文献 683 

Appendix A Verilog Reference 685 

附录A 数的表示和算术电路 685 

A.1 Documentation in Verilog Code 686 

A.1 Verilog代码中的文档 686 

A.2 White Space 686 

A.2 空白符 686 

A.3 Signals in Verilog Code 686 

A.3 Verilog代码中的信号 686 

A.4 Identifier Names 687 

A.4 标识符 687 

A.5 Signal Values, Numbers, and Parameters 687 

A.5 信号值、数值和参数 687 

      A.5.1Parameters 688 

      A.5.1参数 688 

A.6 Net and Variable Types 688 

A.6 线网和变量类型 688 

      A.6.1 Nets 688 

      A.6.1 线网 688 

      A.6.2 Variables 689 

      A.6.2 变量 689 

      A.6.3 Memories 690 

      A.6.3 存储器 690 

A.7 Operators 690 

A.7 操作符 690 

A.8Verilog Module 692 

A.8 Verilog模块 692 

A.9 Gate Instantiations694 

A.9 门实例化 694 

A.10 Concurrent Statements 696 

A.10 并行语句 696 

      A.10.1 Continuous Assignments 696 

      A.10.1 连续赋值 696 

      A.10.2 Using Parameters 697 

      A.10.2 使用参数 697 

A.11 Procedural Statements 698 

A.11 过程语句 698 

      A.11.1 Always and Initial Blocks 698 

      A.11.1 Always和Initial块 698 

      A.11.2 The IfElse Statement 700 

      A.11.2 if else语句 700 

      A.11.3 Statement Ordering 701 

      A.11.3 语句顺序 701 

      A.11.4 The Case Statement 702 

      A.11.4 case语句 702 

      A.11.5 Casez and Casex Statements703 

      A.11.5 Casez和Casex语句703 

      A.11.6 Loop Statements704 

      A.11.6 Loop语句704 

      A.11.7 Blocking versus Nonblocking Assignments for Combinational Circuits 708 

      A.11.7 组合电路的阻塞和非阻塞赋值对比 708  

A.12 Using Subcircuits 709 

A.12 使用子电路 709 

A.12.1 Subcircuit Parameters 710 

      A.12.1 子电路参数 710 

      A.12.2 The Generate Capability 712 

      A.12.2 生成能力 712 

A.13 Functions and Tasks 713 

A.13 函数和任务 713 

A.14 Sequential Circuits 716 

A.14 时序电路 716 

      A.14.1 A Gated D Latch 717 

      A.14.1 门控D锁存器 717 

      A.14.2 D FlipFlop 717 

      A.14.2 D触发器 717 

      A.14.3 FlipFlops with Reset 718 

      A.14.3 带复位的触发器 718 

      A.14.4 Registers 718 

      A.14.4 寄存器 718 

      A.14.5 Shift Registers 720 

      A.14.5 移位寄存器 720 

      A.14.6 Counters 721 

      A.14.6 计数器 721 

      A.14.7 An Example of a Sequential Circuit 722 

      A.14.7 时序电路实例 722 

      A.14.8 MooreType Finite State Machines 723 

      A.14.8 摩尔型有限状态机 723 

      A.14.9 MealyType Finite State Machines 724 

      A.14.9 米利型有限状态机 724 

A.15 Guidelines for Writing Verilog Code 725 

A.15 编写Verilog代码的原则 725 

A.16 Concluding Remarks 731 

A.16 小结 731 

References 731 

参考文献 731 

Appendix B Implementation Technology 733 

附录B实现技术 733 

B.1 Transistor Switches 734 

B.1 晶体管开关 734 

B.2 NMOS Logic Gates 736 

B.2 NMOS逻辑门 736 

B.3 CMOS Logic Gates 739 

B.3 CMOS逻辑门 739 

      B.3.1 Speed of Logic Gate Circuits 746 

      B.3.1 逻辑门电路的速度 746 

B.4 Negative Logic System 747 

B.4 负逻辑系统 747 

B.5 Standard Chips 749 

B.5 标准芯片 749 

      B.5.1 7400Series Standard Chips 749 

      B.5.1 7400系列标准芯片 749 

B.6 Programmable Logic Devices 753 

B.6 可编程逻辑器件 753 

      B.6.1 Programmable Logic Array (PLA) 754 

      B.6.1 可编程逻辑阵列（PLA）754 

      B.6.2 Programmable Array Logic (PAL) 757 

      B.6.2 可编程阵列逻辑（PAL）757 

      B.6.3 Programming of PLAs and PALs 759 

      B.6.3 PLA和PAL的编程 759 

      B.6.4 Complex Programmable Logic Devices (CPLDs) 761 

      B.6.4 复杂可编程逻辑阵列（CPLDs）761 

      B.6.5 FieldProgrammable Gate Arrays 764 

      B.6.5 现场可编程门阵列 764 

B.7 Custom Chips, Standard Cells, and Gate Arrays 769 

B.7 定制芯片、标准单元和门阵列 769 

B.8 Practical Aspects 771 

B.8 实践方面 771 

      B.8.1 MOSFET Fabrication and Behavior 771 

      B.8.1 MOSFET工艺和行为 771 

      B.8.2 MOSFET OnResistance 775 

      B.8.2 MOSFET导通电阻 775 

      B.8.3 Voltage Levels in Logic Gates 776 

      B.8.3 逻辑门中的电平值 776 

      B.8.4 Noise Margin 778 

      B.8.4 噪声容限 778 

      B.8.5 Dynamic Operation of Logic Gates 779 

      B.8.5 逻辑门的动态特性 779 

      B.8.6 Power Dissipation in Logic Gates 782 

      B.8.6 逻辑门的功耗 782 

      B.8.7 Passing 1s and 0s Through Transistor Switches 784 

      B.8.7 通过晶体管开关传输1和0 784 

      B.8.8 Transmission Gates 786 

      B.8.8 传输门 786 

      B.8.9 Fanin and Fanout in Logic Gates 788 

      B.8.9 逻辑门的扇入和扇出 788 

      B.8.10 Tristate Drivers 792 

      B.8.10 三态驱动器 792 

B.9 Static Random Access Memory(SRAM) 794 

B.9 静态随机存取存储器（SRAM）794 

      B.9.1 SRAM Blocks in PLDs 797 

      B.9.1 PLD中的SRAM块 797 

B.10 Implementation Details for SPLDs, CPLDs, and FPGAs 797 

B.10 SPLD、CPLD和FPGA的实现细节 797 

      B.10.1 Implementation in FPGAs 804 

      B.10.1 FPGA实现 804 

B.11 Concluding Remarks 806 

B.11 小结 806 

B.12 Examples of Solved Problems 807 

B.12 问题求解案例 807 

Problems 814 

习题 814 

References 823 

参考文献 823 

Answers 825 

习题答案 825 

Index 839 

索引 839 

Zvonko Vranesic received his B.A.Sc., M.A.Sc., and Ph.D. degrees, all in Electrical Engi-neering, from the University of Toronto. From 1963-1965 he worked as a design engineerwith the Northern Electric Co. Ltd. in Bramalea, Ontario. In 1968 he joined the Univer-sity of Toronto, where he is now a Professor Emeritus in the Departments of Electrical &Computer Engineering and Computer Science. During the 1978-1979 academic year, hewas a Senior Visitor at the University of Cambridge, England, and during 1984—1985 hewas at the University of Paris, 6. From 1995 to 2000 he served as Chair of the Divisionof Engineering Science at the University of Toronto. He is also involved in research anddevelopment at the Altera Toronto Technology Center.PA\His current research interests include computer architecture and field-programmableVLSI technology.PA\He is a coauthor of four other books: Computer Organization and Embedded Systems,6th ed.; Fundamentals of Digital Logic with VHDL Design, 3rd ed., Microcomputer Struc-tures. and Field-Programmable Gate Arrays. In 1990, he received the Wighton Fellowshipfor “innovative and distinctive contributions to undergraduate laboratory instruction.” In2004, he received the Faculty Teaching Award from the Faculty of Applied Science andEngineering at the University of Toronto.PA\He has represented Canada in numerous chess competitions. He holds the ttle ofInternational Master.

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