The book addresses the critical challenges faced by the ever-expanding wireless communication market and the increasing frequency of operation due to continuous innovation of high performance integrated passive devices. The challenges like low quality factor, design complexity, manufacturability, processing cost, etc., are studied with examples and specifics. Silicon on-chip inductor was first reported in 1990 by Nguyen and Meyer in a 0.8 μm silicon bipolar complementary metal oxide semiconductor technology (BiCMOS). Since then, there has been an enormous progress in the research on the performance trends, design and optimization, modeling, quality factor enhancement techniques, etc., of spiral inductors and significant results are reported in literature for various applications. This book introduces an efficient method of determining the optimized layout of on chip spiral inductor.
The important fundamental tradeoffs of the design like quality factor and area, quality factor and inductance, quality factor and operating frequency, maximum quality factor and the peak frequency is also explored. The authors proposed an algorithm for accurate design and optimization of spiral inductors using a 3D electromagnetic simulator with minimum number of inductor structure simulations and thereby reducing its long computation time. A new multilayer pyramidal symmetric inductor structure is also proposed in this book. Being multilevel, the proposed inductor achieves high inductance to area ratio and hence occupies smaller silicon area.

The ever expanding wireless and consumer electronics market necessitates the integration of more and more multiple functions and there is a growing demand for small size, low cost, and high performance circuits. Interestingly today, many wireless applications necessitate the integration of many more multiple functions like phone, video-game console, personal digital assistant, digital camera, web-browser, e-mail, etc. This has presented a challenge to integrate the analog, digital, and radio frequency systems on a single chip. One of the biggest hurdles in the realization of SoC is the integration of the passive components, especially in RF systems. The need for integration of more functionalities has changed the direction in the development of passive components in the last several years. Of the passive devices, the most critical is the inductor.
The performance of CMOS RFICs such as voltage controlled oscillators (VCOs), low noise amplifiers (LNAs), passive element filters, etc., are well determined by the quality of inductors. For example, the quality factor of the inductor determines the stability and phase-noise power of an oscillator for all communication applications and the ability to implement extremely selective filters with a small percentage bandwidth, small shape factor, and low insertion loss. Hence, the design of an inductor is one of the critical steps in the design cycle since the performance and cost will depend on the quality factor and area of the inductor.
The figure of merits of on-chip spiral inductors is determined by their geometrical or layout and the technological parameters. There exist numerous tradeoffs between the performance of a spiral inductor and its design parameters. In most of the performance trend studies reported in the literature, the layout parameters were systematically varied and the corresponding changes in the inductance, quality factor, and resonance frequency were reported. This approach is useful in applications where one has the flexibility to choose from a range of inductance values. However, if a designer targets designing a specified inductance value and optimizes its layout parameters for a particular application, such studies give insufficient information. This is because the quality factor and the inductance follow an opposite trend with the layout parameters. For example, one may attempt to increase the quality factor by increasing the inner diameter to minimize the eddy current effect which however alters the value of inductance. In turn, one can then vary the number of turns, metal width, and spacing to get back the desired inductance value. However, this approach again alters the quality factor but this need not be the optimum value at the desired frequency. Therefore, in this book, the importance of studying the performance trend by varying the layout parameters keeping the inductance value constant is discussed in detail.
Inductors are generally designed either based on a library of previously available fabricated inductors or using an electromagnetic simulator. The former method limits the design space and the latter is computationally expensive and time consuming. A typical spiral inductor design problem is to determine the layout parameters that results in the desired inductance value. For a desired inductance value, a number of possible combinations of these parameters exist. Therefore, it is imperative to find the optimized parameters for a particular inductance that results the highest Q at desired frequency. In this book, a simple method to determine the optimum layout parameters is described which can shorten the design and product time-to-market cycle.
Generally, inductors may be optimized using enumeration or numerical methods. The enumeration methods are simple and can find a nearly global optimum design but highly inefficient. On the other hand, numerical methods have proven to be more efficient in reducing the computation time by converging rapidly to the optimal design. However, such algorithms result in a single set of inductor design parameters and no information is available to the extent the other combinations are from the optimal one. Information about the near optimal solution is also important to judiciously explore the tradeoff between the different competing figure of merits. The efficiency and the result of optimizing all such methods requires the knowledge of performance trends of the inductor with its layout parameters in order to decide the design search space. If the designer is not well acquainted with the complexity of inductor design, the design parameter constraints may include sets of unfeasible specifications which will increase the number of function evaluations and computation time unnecessarily. For example, a large search space may be defined which will require huge computation time or a small search space may be defined where the solution may not be globally optimum. Furthermore, this book discusses the methodology to find the bounds of optimization constraints and restricts the search to the feasible region and promotes fast convergence to a solution. The incorporation of a bounding method with an optimization schedule will definitely speed up the optimum inductor synthesis.
Inductors are also designed using an electromagnetic simulator. This method is computationally expensive and time consuming due to which design methods based on lumped element model are generally adopted. A lumped element model however gives only an approximate electrical characteristic and the result may also be prone to errors. Verification of the design using a full wave EM simulator is therefore required before fabrication. Sometimes the designer may even be compelled to repeat the entire design when such errors are not tolerable. Therefore, optimization using an EM simulator would be more advantageous. But a method using an EM simulator would be acceptable only if a few structures have to be simulated. In this book, we have shown that this can be made possible by identifying the optimum width and the number of turns from the simulation of a few structures. If these few structures can be identified, then the optimized design parameters can be determined most accurately using an EM simulator.
In most of the integrated circuits like amplifiers, mixers, oscillators, etc., the differential topology is preferred because of its less sensitivity to noise and interference. For such applications, symmetric inductors are preferred because under differential excitation, quality factor and self-resonance frequency increases. Generally, a pair of asymmetric planar inductors connected together in series or the conventional symmetric inductor is used, notwithstanding the area occupied, which is very large. With technology scaling, the number of metal layers is increasing and taking advantage of this; in this book, a new multilayer inductor is discussed to improve the performance of on-chip inductors. Further, its performance is demonstrated by fabricating and characterizing the inductors. The structure is implemented in an application circuit and performance is illustrated by test and measurement results.
Chapter 1 discusses the design of on-chip inductor with a review of its innovative structure evolution and design trends, followed by a discussion of the unsolved problems.
Chapter 2 exemplifies the importance to study the performance trend more systematically, keeping the inductance constant and varying the layout parameters. This study will lead to promising conclusions that in turn would help optimizing inductors more efficiently. Also, a method of bounding the layout design parameters is proposed, thereby limiting the feasible design search space and hence optimization can be carried out efficiently. Performance characterization using an EM simulator is more accurate compared to a lumped element model. This chapter also suggests a method to identify only the few nearly optimum structures and finds the most optimized design parameters using an EM simulator.
In Chap. 3, a multilayer spiral inductor is proposed, in which the traces of the metal spiral up and down in a pyramidal manner exploits the multiple metal layers. This structure is discussed extensively with the development of a lumped element model and calculation of its parasitic capacitance to predict its self resonance frequency. It is also shown that this form of spiraling results in lower parasitics. The performance trends of this new inductor with its layout parameters are also investigated. The structure is also symmetric and it is illustrated that, for differential circuit implementations, the area of the chip can be reduced to a large extent as compared to its equivalent conventional inductors. The layout, fabrication and measurement results of the inductor are also reported in detail.
Chapter 4 discusses the design of an LC differential VCO employing the proposed inductor in the LC tank. The design process of the tank inductor and the capacitor is explained. A prototype of the VCO is implemented in 0.18 lm UMC RF CMOS technology. The performance of the VCO is investigated by simulation and validated by the testing and measurement results.
March 2013 Genemala Haobijam
Roy Paily Palathinkal

1 Introduction 1

1.1 Silicon Integrated Passive Devices 1

1.2 On-Chip Inductor 2

1.3 Review of Si On-Chip Inductor Design and Optimization 9

      1.3.1 Spiral Inductor Structures 10

      1.3.2 Quality Factor Enhancement Techniques 15

      1.3.3 Inductor Design and Optimization Methods 16

1.4 Summary 16

References 17

2 Optimization of Spiral Inductor with Bounding of Layout Parameters 21

2.1 Introduction 21

2.2 Bounding of Layout Parameters 22

2.3 Performance Study of Fixed-Value Inductors Using EM Simulator 28

      2.3.1 Area of the Inductor 28

      2.3.2 Quality Factor Variation with the Number of Turns 30

      2.3.3 Quality Factor Variation with the Metal Width 31

      2.3.4 Quality Factor Variation with the Spacing Between the Metal Tracks 34

2.4 Efficient Optimization with Bounding of Layout Parameters 36

      2.4.1 Lumped Element Model of a Planar Spiral Inductor 37

      2.4.2 Calculation of Figure of Merits 38

      2.4.3 Performance Evaluation with an Optimization Example 38

      2.4.4 Computational Speed 43

      2.4.5 Global Optimal Quality Factor Tradeoff Curve 44

      2.4.6 Peak Quality Factor Variation with Inductance 46

2.5 Optimization Using EM Simulator 46

2.6 Summary 49

References 50

3 Multilayer Pyramidal Symmetric Inductor 53

3.1 Introduction 53

3.2 Design of MPS Inductor Structure 54

3.3 Lumped Element Model of the MPS Inductor Structure 56

3.4 Parasitic Capacitance Calculation for Conventional Multilayer Symmetric Inductor 60

3.5 Characterization of the MPS Inductor Structure 64

      3.5.1 Performance Trend of MPS Inductors 65

      3.5.2 Comparison of MPS with Its Equivalent Planar Inductor Structures 70

      3.5.3 Comparison of MPS with Multilayer Conventional Symmetric and Asymmetric Stack Structures 72

3.6 Experimental Verification 76

      3.6.1 Process Parameters 76

      3.6.2 Layout of MPS Inductors 76

      3.6.3 Deembedding Process 78

      3.6.4 Measured Results and Discussion 81

3.7 Summary 83

References 84

4 Implementation of the MPS in Voltage Controlled Oscillator 87

4.1 Introduction 87

4.2 Passive Elements of the LC Tank 88

      4.2.1 Inductor Design 88

      4.2.2 Varactor Design 91

4.3 VCO Circuit Design 93

4.4 VCO Simulation 95

4.5 Measurement Results and Discussion 98

4.6 Summary 102

References 102

About the Author 103

Index 105

Prof. Roy Paily received his B.Tech. degree in Electronics and Communication Engineering from College of Engineering, Trivandrum, India in 1990. He obtained the M.Tech. and Ph.D. from Indian Institute of Technology Kanpur and Indian Institute of Technology Madras in 1996 and 2004 respectively, in the area of Semiconductor Devices. Presently, he is working as a Professor in the Department of Electronics and Electrical Engineering, Indian Institute of Technology Guwahati. Before joining academia, he worked as a Process Engineer in a hard disk manufacturing company. His research interests are VLSI devices/circuits and MEMS, and has published about 100 articles in journals and conferences. His team has taped out two silicon CMOS chips though Europractice IC Service under a Research and Development project "Special Manpower Development Project in VLSI Design and Related Software" sponsored by DIT, India. He has developed a web-based course, "Integrated Circuits Technology" under National program on Technology Enhanced Learning. “Digital VLSI Design Virtual Lab" is another online course developed through the initiative of MHRD. He is a member of IEEE and VLSI Society of India and a life member of ISSS and IETE.

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