Since its first volume in 1960, Advances in Computers has presented detailed coverage of innovations in computer hardware, software, theory, design, and applications. It has also provided contributors with a medium in which they can explore their subjects in greater depth and breadth than journal articles usually allow. As a result, many articles have become standard references that continue to be of significant, lasting value in this rapidly expanding field.
Key Features
In-depth surveys and tutorials on new computer technology
Well-known authors and researchers in the field
Extensive bibliographies with most chapters
Many of the volumes are devoted to single themes or subfields of computer science

Traditionally, Advances in Computers, the oldest series to chronicle the rapid evolution of computing, annually publishes several volumes, each typically comprised of four to eight chapters, describing new developments in the theory and applications of computing. The theme of this 96th volume is inspired by the advances in computer architecture. Within the spectrum of computer architecture, this volume concentrates on dataflow processing, heterogeneous and reconfigurable architecture, and caching. The volume is a collection of five chapters that were solicited from authorities in the field, each of whom brings to bear a unique perspective on the topic.
In Chapter 1 "An Overview of Selected Heterogeneous and Recon-figurable Architectures, " Stojanovic et al. introduce and articulate the moti-vations behind heterogeneous and reconfigurable architectures. A classical classification of heterogeneous architectures and the extended Flynn's tax-onomy are discussed. The authors then introduce a new classification based on the computational model, i.e., control flow and dataflow model of com-putations. Several commercially available heterogeneous platforms (CBEA, Clear Speed, SGI RASC, Convey, Maxeler Max Nodes, NVidia GPU, and AMD ATI GPU) are studied and comparatively analyzed. Finally, three sys-tems, namely, Intel Core i7-870 CPU with 4 cores, NVidia C2070 GPU, and Maxeler MAX3 cardas typical representative of CPU, GPU, and Dataflow computing model have been experimentally studied and com-pared against each other.
In Chapter 2 "Concurrency, Synchronization, and Speculation—The Dataflow Way, "Kavi etal. survey the evolution of dataflow processing. Dataflow model of computation is introduced and its advantages in terms of concurrency, synchronization, and speculation relative to control flow computation are addressed. The chapter then studies several dataflow lan-guages, historical architectures, and recent architectures. Finally,the so-called scheduled dataflow architecture which applies dataflow execution model at the thread level as a case study is discussed in detail
Application targeting reconfigurable architecture (see Chapter 1 "An Overview of Selected Heterogeneous and Reconigurable Architectures" ) can exploit inherent fine-grained parallelism and predictable low latency fea-tures on the underlying platform to achieve high throughput per watt. However, traditional techniques for designing FPGA (Field Programmable Gate Array) -based reconfigurability are time consuming and hence have limited commercial attraction. To overcome this handicap, Maxeler Technology has developed a dataflow-based platform based on earlier static synchronous dataflow architecture (see Chapter 2 "Concurrency, Synchro-nization, and Speculation—The Dataflow Way" ) enhanced by datastream-ing. In Chapter 3 "Dataflow Computing in Extreme Performance Conditions, "Oriato et al. discuss about the Maxeler dataflow engine and show its practicality in a case study for a complex atmospheric simulation. It is shown that in comparison to the conventional technologies, a perfor-mance improvement by two orders of magnitude is possible.
Chapter 4 "Sorting Networks on Maxeler Dataflow Super computing Systems" by Kos et al. is intended to show the application of dataflow par-a dig min general, and Maxeler dataflow computer in particular, in handling a popular and classical problem, i.e., sorting. The chapter gives a short survey on sorting algorithms. Several classes of sorting algorithms, i.e., sequential sorting algorithms, parallel sorting algorithms, and sorting networks, along with their comparative analysis are discussed. The chapter then focuses on sorting networks and discusses its suitability for dataflow paradigm and its implementation on the Maxel er platform. Experimental results are detailed and analyzed.
Finally, in Chapter 5"Dual Data Cache Systems: Architecture and Analysis, "Sustran et al. open up the discussion about dual data cache systems in which the data cache is split into two subsystems based on the data access patterns. The advantages of dual cache systems are articulated and a classifi-cation of the proposed schemes as advanced in the literature is introduced. The proposed approaches are studied in detail and critically based on speed, complexity, and power consumption analyzed. The so-called Split Temporal/Special Data Cache (STS) design is extensively studied and analyzed.
We hope that you find these chapters of interest, and useful in your teaching, research, and other professional activities. We welcome feedback on the volume, and suggestions for topics for future volumes.
ALI R. HURSON
Rolla, MO, USA
and
VELJKO MILUTINOVIC
Belgrade, Serbia

1. An Overview of Selected Heterogeneous and Reconfigurable Architectures 1

Sasa Stojanovic, Dragan Bojic, and Miroslav Bojovic

1 Introduction 3

2 Problem Statement 4

3 Existing Solutions and Their Criticism 5

4 Summary of Presented Solutions 28

5 Performance Comparison of Presented Solutions 35

6 Conclusion 40

Acknowledgments 41

References 42

About the Authors 44

2. Concurrency, Synchronization, and Speculation—The Dataflow Way 47

Krishna Kavi, Charles Shelor, and Domenico Pace

1 Introduction 49

2 Dataflow Concepts 50

3 Dataflow Languages 56

4 Historical Dataflow Architectures 65

5 Recent Dataflow Architectures 77

6 Case Study: Scheduled Dataflow 89

7 Conclusions 99

References 101

About the Authors 103

3. Dataflow Computing in Extreme Performance Conditions 105

Diego Oriato, Stephen Girdlestone, and Oskar Mencer

1 Introduction 106

2 Dataflow Computing 108

3 Maxeler Multiscale DFEs 110

4 Development Process 112

5 Programming with MaxCompiler 114

6 Dataflow Clusters 119

7 Case Study: Meteorological Limited-Area Model 123

8 Conclusion 135

References 136

About the Authors 136

4. Sorting Networks on Maxeler Dataflow Supercomputing Systems 139

Anton Kos, Vukasin Rankovic, and Saso Tomazic

1 Introduction 140

2 Motivation 141

3 Sorting Algorithms 143

4 Sorting Networks 150

5 Implementation 163

6 Setting Up the Experiment 169

7 Experimental Results 171

8 Conclusion 183

References 184

About the Authors 185

5. Dual Data Cache Systems: Architecture and Analysis 187

Zivojin Sustran, Goran Rakocevic, and Veljko Milutinovic

1 Introduction 188

2 A DDC Systems Classification Proposal 190

3 Existing DDC Systems 191

4 Conclusion of the Survey Part 215

5 Problem Statement for the Analysis 217

6 Critical Analysis of Existing Solutions 217

7 Generalized Solution 218

8 Determining Locality 221

9 Modified STS in a Multicore System 224

10 Conditions and Assumptions of the Analysis Below 224

11 Simulation Strategy 225

12 Conclusions of the Analysis Part 230

13 The Table of Abbreviations 230

Acknowledgments 232

References 232

About the Authors 233

Author Index 235

Subject Index 241

Contents of Volumes in this Series 247

A. R. Hurson is currently a professor and Chair of Computer Science department at Missouri S&T. Before joining Missouri S&T, he was a professor of Computer Science and Engineering department at The Pennsylvania State University. His research for the past 30 years has been directed toward the design and analysis of general as well as special purpose computer architectures. His research has been supported by NSF, DARPA, the Department of Education, the Air Force, the Office of Naval Research, Oak Ridge National Laboratory, NCR Corp., General Electric, IBM, Lockheed Martin, Pennsylvania State University, and Missouri S & T. He has published over 300 technical papers in areas including multidatabases, global information sharing and processing, application of mobile agent technology, object oriented databases, mobile and pervasive computing environment, sensor and ad-hoc networks, computer architecture and cache memory, parallel and distributed processing, dataflow architectures, and VLSI algorithms. Dr. Hurson served as the Guest Co-Editor of special issues of the IEEE Proceedings on Supercomputing Technology, the Journal of Parallel and Distributed Computing on Load Balancing and Scheduling, the journal of integrated computer-aided engineering on multidatabase and interoperable systems, IEEE Transactions on Computers on Parallel Architectures and Compilation Techniques, Journal of Multimedia Tools and Applications, and Journal of Pervasive and Mobile Computing. He is the co-author of the IEEE Tutorials on Parallel Architectures for Database Systems, Multidatabase systems: An advanced solution for global information sharing, Parallel architectures for data/knowledge base systems, and Scheduling and Load Balancing in Parallel and Distributed Systems. He is also the guest Editor of advances in computers for Parallel, Distributed, and Pervasive Computing. Hurson is the Co-founder of the IEEE Symposium on Parallel and Distributed Processing (currently IPDPS) and IEEE conference on Pervasive Computing and Communications. Professor Hurson has been active in various IEEE/ACM Conferences and has given tutorials and invited lectures for various conferences and organizations on global information sharing, database management systems, supercomputer technology, data/knowledge-based systems, dataflow processing, scheduling and load balancing, parallel computing, and Pervasive computing. He served as a member of the IEEE Computer Society Press Editorial Board, an IEEE Distinguished speaker, editor of IEEE transactions on computers, editor of Journal of Pervasive and Mobile Computing, and IEEE/ACM Computer Sciences Accreditation Board. Currently, he is serving as an ACM distinguished speaker, area editor CSI Journal of Computer Science and Engineering, and Co-Editor-in-Chief Advances in Computers.

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