This work will educate chip and system designers on a method for accurately predicting circuit and system reliability in order to estimate failures that will occur in the field as a function of operating conditions at the chip level. This book will combine the knowledge taught in many reliability publications and illustrate how to use the knowledge presented by the semiconductor manufacturing companies in combination with the HTOL end-of-life testing that is currently performed by the chip suppliers as part of their standard qualification procedure and make accurate reliability predictions. This book will allow chip designers to predict FIT and DPPM values as a function of operating conditions and chip temperature so that users ultimately will have control of reliability in their design so the reliability and performance will be considered concurrently with their design.
Key Features
The ability to include reliability calculations and test results in their product design
The ability to use reliability data provided to them by their suppliers to make meaningful reliability predictions
Have accurate failure rate calculations for calculating warrantee period replacement costs

Introduction ix

Chapter 1 Shortcut to Accurate Reliability Prediction 1

1.1 Background of FIT 3

1.2 Multiple Failure Mechanism Model 5

1.3 Acceleration Factor 6

1.4 New Proportionality Method 9

1.5 Chip Designer 10

1.6 System Designer 13

Chapter 2 M-HTOL Principles 15

2.1 Constant Rate Assumption 15

2.2 Reliability Criteria 17

2.3 The Failure Rate Curve for Electronic Systems 19

2.4 Reliability Testing 21

2.5 Accelerated Testing 25

Chapter 3 Failure Mechanisms 31

3.1 Time-Dependent Dielectric Breakdown 31

3.2 Hot Carrier Injection 38

3.3 Negative Bias Temperature Instability 42

3.4 Electromigration 44

3.5 Soft Errors Due to Memory Alpha Particles 47

Chapter 4 New M-HTOL Approach 49

4.1 Problematic Zero Failure Criteria 50

4.2 Single Versus Multiple Competing Mechanisms 54

4.3 AF Calculation 56

4.4 Electronic System CFR Approximation/Justification 65

4.5 PoF-Based Circuits Reliability Prediction Methodology 76

4.6 Cell Reliability Estimation 83

4.7 Chip Reliability Prediction 87

4.8 Matrix Method 88

Bibliography 93

Joseph B. Bernstein is Professor of Electrical Engineering at Ariel University, Ariel, Israel. He received his PhD from MIT, Cambridge, MA, USA, and has previously worked as a Professor at Bar Ilan University, Israel, and at the University of Maryland and the MIT Lincoln Laboratory. He has co-authored two books.

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